Analog-to-digital converters (ADCs) utilize sampling circuitry that samples an analog input signal at points in time and, then, converts the samples to digital values to create a digital signal. The use of ADCs is common in applications that involve receiving an input signal or input data represented by an analog signal, and then operate to convert the analog signal to a digital signal for further processing in a digital form. In order to convert an analog input signal accurately, the sampling of the input signal performed by the sampling circuitry should be accomplished so that it provides samples to the converter, which represent an analog input signal with as much precision as feasible. As the frequency of an analog input signal (Fin) to be converted increases, the necessary frequency of sampling also increases. As the number of the types of applications in which ADCs are used has increased, there has also been an increase in the need for ADCs capable of operation at increasingly higher speeds of operation.
Time interleaved ADCs, which utilize multiple channels to process an analog input signal on a time interleaved basis, are a type of ADC that has been developed for high-speed applications, high-speed implementations, etc. Interleaving can also lower the power consumption for a given resolution. This is because, as the sampling rate of single-channel ADCs approaches the limits of the technology used, the speed/power trade-off of the single-channel ADCs becomes nonlinear: making interleaving an attractive alternative. If a sufficient number of ADC channels are interleaved, then each bears a linear speed/power trade-off and, hence, reaches an optimum framework. The overhead associated with interleaving should also be taken into account in assessing the overall performance of any system. Additionally, for resolutions of roughly 8 bits and above, the mismatches among the channels, for example timing mismatches between the samples on each of the interleaved channels, should be removed. This may be done, for example, via foreground or background calibration.
Time interleaved ADCs effectively provide a speed advantage in the sampling rate of digital to analog conversion over single channel ADCs, since the conversion rate increases proportionally with the number of channels. In a time interleaved ADC, each channel is able to sample the analog input signal in turn. With N Channels operating in parallel, the sampling rate increases by the factor N over that of a single channel ADC. During a time in which a sample is being taken from one channel, samples from the other channels may be processed. The time interleaved ADCs, therefore, generate digital code words at higher rates than a single channel system. However, a drawback of time interleaved ADCs is that errors can arise because of mismatches between the different channels. Interleaved technology is sensitive to timing mismatches between the channels.
Hence, in addition to raising the conversion speed, interleaving also reduces the metastability rate making an ADC more stable. Since each channel is given a longer time for conversion, the probability of metastability drops exponentially. In a general sense, the performance of interleaved ADCs is typically limited by mismatches among the channels. Gain, offset, and timing mismatches heavily impact the overall signal-to-(noise+distortion) ratio (SNDR) at resolutions of 8 bits or higher. Often times, the timing mismatch is the most difficult to calibrate because it does not easily lend itself to detection or correction.
In a typical time interleaved sampling ADC, sampling signals are used to control the timing of sampling on each of the interleaved channels of the ADC. A track and hold circuit can be used to track (and then take) a sample of the analog input signal from a channel when the sampling signal changes from one state to another: triggering a switch to hold a sample of the analog input signal. Any mismatches between the switches and any timing mismatches between the edges of the sampling signals cause the sequence of interleaved samples from the interleaved channels to be non-uniformly spaced in time. The non-uniform spacing of the samples results in the appearance of undesired spectral components in the output sequence of the sampling system. These spectral components typically produce images of the desired sampled signal and, frequently, occur at undesired locations in the output spectrum. For example, in a simple two-way interleaved system, timing mismatches in the sample clocks can result in images of the desired signal appearing at Fs/2 +/−Fin, where Fs is the sampling frequency of the system and Fin is the frequency of the input signal to the system. The magnitudes of the images are proportional to the time difference between sampling channels, and also proportional to the frequency of the input signal. These errors degrade the maximum achievable spurious-free dynamic range (SFDR) of the sampling system, especially at higher input frequencies.
Reducing the effects of the spectral artifacts caused by timing mismatch is costly. Large digital filters, which consume significant power, can be used. Alternately, lower-power analog circuits can be used to “trim” the timing errors to a small value. However, in either case, the degree to which the errors can be reduced below an acceptable level and maintained at the acceptable level [despite ambient changes in supply, temperature, die stress, etc.,] can depend on how small the errors are initially. Small initial errors tend to remain small, while large initial errors can be reduced by trimming, but tend to drift significantly as ambient changes occur.
Because timing errors are so difficult to remove, systems often utilize some form of randomization of the sampling networks by using additional networks. This does not remove the impact of the timing errors. The randomization simply distributes the errors more randomly in time, rather than in a fixed pattern. This tends to spread the errors into the noise floor of the system. This action increases the noise floor of the system and, further, degrades the maximum signal-to-noise ratio (SNR) that the sampling system can achieve. Minimizing the timing errors, therefore, maximizes the potential signal-to-noise ratio (SNR) that the system can achieve. This is true even when randomization is also used. A system with a small initial timing error provides an advantage in any time interleaved ADC system. Therefore, it would be desirable to have a solution that minimized the timing mismatch in a time interleaved ADC that required reduced complexity to implement, that was relatively simple to implement, and that could be used by itself or in combination with other techniques.
Overview
The present disclosure relates generally to an apparatus, a system, circuitry, and a method for generating sampling signals for controlling a sampling system. In an example embodiment, the method, system, and apparatus may comprise circuitry that generates outputs as sampling clocks for a time interleaved sampling circuit having multiple interleaved sampling channels. The circuitry may be implemented such that common circuitry is shared between the sampling clock circuitry of each of the multiple interleaved channels. Utilization of the common circuitry allows uniform control of the timing relationship between the sampling clocks relative to one another. Such an approach can reduce the timing skew between the sampling clocks. In example implementations of the embodiments, the multiple interleaved sampling channels may comprise the interleaved sampling channels of an analog-to-digital converter (ADC) circuit.
In one embodiment, a circuit for receiving a plurality of input signals including an input clock signal, and generating a plurality of sampling clocks, is provided. The circuit comprises first circuitry configured to selectively set each sampling clock of the plurality of sampling clocks to a first output state, wherein a selected sampling clock of the plurality of sampling clocks is set to the first output state when a selected input of the plurality of input signals is set to a first input state. The circuit also comprises second circuitry configured to transition each of the plurality of sampling clocks to a second output state, through a common path, wherein the selected sampling clock is transitioned from the first output state to the second output state through the common path in response to a transition of the input clock signal from a first to a second clock state.
In another embodiment, the circuit may comprise boost circuitry to generate boosted outputs as sampling clocks for a time interleaved sampling circuit. The boosted sampling clocks provide a higher signal level for turning on the switches that are driven by the sampling clock outputs. The circuitry can be implemented such that common circuitry may be shared between the sampling clock circuitry of each of the multiple interleaved channels. Utilization of the common circuitry can allow for a uniform control of the timing relationship between the boosted sampling clocks.
In yet another embodiment, the circuit may include a sampling circuit that includes a plurality of sampling channels each coupled to an output of the first circuitry corresponding to one of the plurality of sampling clocks. The sampling circuit may be configured to generate a sample from a selected channel of the plurality of channels when the selected sampling clock is transitioned to the second output state from the first output state.
In another example embodiment, the method, system, and apparatus comprises circuitry to generate outputs as sampling clocks for an time interleaved sampling circuit that includes a structure that minimizes timing skew between the sampling clocks by utilizing a common clock signal that controls pull-up/hold-down circuitry that may be shared between the sampling clock circuitry of each of the multiple interleaved channels. Utilization of the common pull-up/hold-down circuitry allows control of the timing relationship between the edges of the sampling clocks of the multiple interleaved channels relative to one another to minimize clock skew. In this implementation of the pull-up/hold-down circuitry, the sampling clocks may be boosted.
In other example embodiments, the method, system, and apparatus comprises circuitry to generate outputs as sampling clocks for an time interleaved sampling circuit that may include structure that minimizes timing skew between the sampling clocks by utilizing a common clock signal. The common clock signal controls pull-up/hold-down circuitry and pull-down circuitry that may be shared between the sampling clock circuitry of each of the multiple interleaved channels. Utilization of the common pull-up/hold-down circuitry and pull-down circuitry allows control of the timing relationship between the edges of the sampling clocks of the multiple interleaved channels (relative to one another) to minimize clock skew. In an example implementation of the embodiment of the pull-up/hold-down circuitry and pull-down circuitry, the sampling clocks may be boosted.